AMD Unveils Spartan UltraScale+ Programmable Logic Chips Designed for Edge Computing Applications

AMD has unveiled its Spartan UltraScale+ programmable logic chips, specifically designed for cost-sensitive edge applications.

The company, based in Santa Clara, California, released these advanced field programmable gate arrays (FPGAs) as part of its $49 billion acquisition of Xilinx. The new chips are engineered to offer high input/output (I/O) counts, enhanced power efficiency, and robust security features, making them suitable for a variety of industries, including embedded vision, healthcare, industrial networking, robotics, and video.

"Our sixth generation of Spartan FPGA product line continues to be one of the most widely used in the industry," stated Rob Bauer, senior manager of product marketing at AMD, during a recent press briefing. "Spartan FPGAs empower technology from everyday devices to groundbreaking innovations."

The Spartan UltraScale+ chips signify a technological advancement in FPGAs, boasting the highest I/O to logic cell ratio in devices produced on 28-nanometer (nm) manufacturing processes. They offer up to 30% lower total power consumption and improved performance compared to their predecessors.

"For over 25 years, the Spartan FPGA family has played a crucial role in many of humanity's key innovations, from lifesaving automated defibrillators to the CERN particle accelerator,” remarked Kirk Saban, corporate vice president at AMD’s Adaptive and Embedded Computing Group. “The Spartan UltraScale+ family builds on proven 16nm technology and enhances security and design capabilities, reinforcing our commitment to delivering cost-effective solutions for our customers.”

Flexible I/O and Power Efficiency

Tailored for edge computing, the Spartan UltraScale+ FPGAs provide high I/O counts and adaptable interfaces for seamless integration with various devices. With support for up to 572 I/Os and voltages of up to 3.3V, they facilitate versatile connectivity for edge sensing and control applications. Their 16-nm architecture and various packaging options ensure high I/O density in a compact form factor.

These FPGAs potentially reduce power consumption by up to 30% compared to the 28nm Artix 7 family by using 16nm FinFET technology. They feature a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, ensuring power efficiency and readiness for future applications.

Security is a critical aspect of edge applications, and Spartan UltraScale+ FPGAs come equipped with features like Post-Quantum Cryptography using NIST-approved algorithms, providing robust intellectual property protection against evolving cyber threats. Each device features a physical unclonable function, granting it a unique fingerprint for added security.

"With the increase in edge devices collecting more data, user privacy and intellectual property protection have become essential," Bauer noted. "Security is now a fundamental requirement for our customers."

To mitigate the risk of tampering, the chips support PPK/SPK key management, helping to manage obsolete or compromised keys. They also employ differential power analysis for protection against side-channel attacks and feature a permanent tamper penalty to prevent misuse. Enhanced resilience against single-event upsets ensures rapid and reliable configuration.

The entire AMD FPGA lineup, including the Spartan UltraScale+ family, is supported by the AMD Vivado Design Suite and Vitis Unified Software Platform. This integration allows designers to benefit from increased productivity throughout the design and verification processes.

Sampling and evaluation kits for the Spartan UltraScale+ FPGA family are scheduled for release in the first half of 2025, with immediate access to documentation. Tool support is expected to begin in the fourth quarter of 2024. The Spartan line was originally launched in 1998.