Applied Materials Unveils Innovations in Chip Wiring for Energy-Efficient Computing
Applied Materials has introduced groundbreaking advancements in chip wiring aimed at overcoming challenges posed by energy-efficient computing.
The integration of new materials into chip wiring enhances the manufacturing process at the two-nanometer node, where circuit widths measure a mere two billionths of a meter apart. This innovation is expected to decrease wiring resistance by up to 25% and lower chip capacitance by as much as 3%.
Progress in Chip Manufacturing
Chip manufacturers are already implementing these advancements in logic chips, while memory chip makers, particularly those focusing on dynamic random access memory (DRAM), are assessing improvements for enhanced 3D chip stacking. The ultimate goal is to support the production of a trillion-transistor chip, such as a graphics processing unit (GPU), as reported in IEEE Spectrum. The industry seeks to meet the demands of Moore’s Law, which predicts that the number of components on a chip doubles roughly every two years. Instead of simply shrinking in size, chips are increasingly becoming larger, with multiple chips integrated into single solutions through advanced packaging techniques.
Remarkably, the chip industry has achieved a threefold improvement in performance every two years for the last 15 years. Continued innovation in materials, as noted by Alex Jansen, director of product marketing at Applied Materials, is essential. “To continue this trajectory, new materials must be developed across various areas: patterning, transistors, wiring, and advanced packaging. Our current focus is on wiring,” Jansen stated.
The Importance of Wiring
Modern chips feature more than 60 miles of copper interconnects, comprising 18 metal layers and four or five critical layers. Jansen describes each chip as a complex 3D network of wires.
At the Semicon West event in San Francisco, Applied Materials showcased its advancements in semiconductor manufacturing equipment. The company emphasized that material engineering innovations aim to heighten the performance-per-watt of computer systems by facilitating copper wiring scalability to the 2nm logic node and beyond.
“The AI era necessitates more energy-efficient computing, with chip wiring and stacking playing critical roles in performance and power consumption,” said Prabu Raja, president of the Semiconductor Products Group at Applied Materials. “Our latest integrated materials solution allows the industry to scale low-resistance copper wiring to emerging angstrom nodes while our new low-k dielectric material decreases capacitance and enhances chip integrity for advanced 3D stacking.”
Addressing Moore's Law Challenges
Applied Materials is leveraging a Ruthenium Cobalt liner to enhance wiring performance. Cutting-edge logic chips today can possess tens of billions of transistors connected by extensive microscopic copper wiring. Each wiring layer initiates with a thin film of dielectric material, which is then etched to create channels filled with copper.
For decades, low-k dielectrics and copper have been the standard combination, driving advances in scaling, performance, and power efficiency with each new generation. Nonetheless, as the industry progresses to 2nm and below, thinner dielectric materials compromise chip mechanical strength, while narrowing copper wires can significantly raise electrical resistance, consequently hindering chip performance and increasing power consumption.
Enhanced Low-k Dielectric for Improved Performance
Applied Materials’ Endura CVD machines are playing a crucial role in enhancing chip wiring. The company’s Black Diamond material has led the industry for years by enveloping copper wires in a low-dielectric-constant film, specifically engineered to minimize electrical charge buildup, which heightens power consumption and signal interference.
Recently, Applied introduced an upgraded version of Black Diamond, marking a significant leap in engineering. This new material, an Enhanced Black Diamond, reduces the minimum k-value, enabling scalability to 2nm and beyond while simultaneously bolstering mechanical strength critical for advancing 3D logic and memory stacking.
Ajay Bhatnagar, managing director of product marketing, expressed enthusiasm about the advancements, highlighting the material’s role in shoring up trenches and insulating wires from binary materials. “This matrix surrounds the copper wiring with a specially engineered low-k dielectric to mitigate electrical charge buildup and interference,” Bhatnagar explained.
Innovative Binary Metal Liner for Copper Wiring
Applied Materials is pushing the boundaries of Moore’s Law by integrating its latest Integrated Materials Solution (IMS), combining six different technologies within one high-vacuum system. The innovative binary metal combination of Ruthenium and Cobalt (RuCo) not only reduces the thickness of the liner by 33% to 2nm but also optimizes surface properties for void-free copper deposition, resulting in reduced electrical line resistance and improved chip performance.
As copper wiring dimensions shrink, voids can form during the fabrication process, heightening resistance and compromising yield. The transition to a Ruthenium and Cobalt liner offers greater space for copper, enhancing the effective wiring width and lowering resistance. The new Applied Endura Copper Barrier Seed IMS, featuring Volta Ruthenium CVD, has garnered adoption from leading logic chipmakers and has begun shipping for the 3nm node.
Industry Responses
Sunjung Kim, VP and head of foundry development at Samsung Electronics, noted the importance of material engineering innovations in overcoming interconnect wiring resistance and reliability challenges. “While patterning advancements are crucial, there are still significant hurdles in interconnect wiring,” Kim stated.
Y.J. Mii, EVP and co-COO at TSMC, highlighted the semiconductor industry’s need to enhance energy-efficient performance to support sustainable growth in AI computing. “Innovations that reduce interconnect resistance will play a vital role in overall system performance and efficiency,” Mii emphasized.
The Future of Chip Wiring
Applied Materials is the leading force in chip wiring process technologies. The intensification of interconnect wiring steps from the 7nm to the 3nm node has expanded Applied’s market opportunity by over $1 billion per 100,000 wafer starts per month, raising the total to approximately $6 billion. Anticipated advancements in backside power delivery could further enhance this opportunity by an additional $1 billion per 100K WSPM, pushing the total to about $7 billion.
Intel's recent research highlights a focus on improving wiring through the chip's backside, enabling thicker power lines while supplementing necessary improvements on the frontside. These simultaneous advancements simplify routing, yielding enhanced performance and power efficiency.
Historically, the industry has shifted from aluminum to dielectrics and copper for wiring materials, continually seeking stronger, energy-efficient wires. With ongoing innovations, the barriers in chip designs that hinder electrical conductivity are being addressed.
“We are striving to optimize wire usage while minimizing resistance as features shrink and wiring spaces become constrained,” Jansen remarked. “Electrical crosstalk and signal distortion can hinder performance and power consumption, countering our objectives.”
As demand for advanced AI chips rises, ongoing improvements in performance and efficiency are critical. The latest developments in chip wiring will be featured in Applied’s upcoming Semicon West 2024 Technology Breakfast.
Conclusion: Advancing GPU and AI Chip Performance
Ultimately, these innovations are geared towards enhancing GPUs and AI chips, ensuring they meet future computational demands. According to Applied Materials representatives, these advancements will help maintain the trajectory of achieving threefold improvements in energy efficiency every two years.
“This technology is essential for scaling to 2nm and beyond,” Jansen asserted. Bhatnagar noted that high mechanical strength is crucial for 3D stacking, necessary for efficiently meeting AI processing needs without overheating. “We are enlightening our materials to meet the high-bandwidth memory demands of AI,” Bhatnagar remarked.
As Jansen concluded, “Our efforts align with extending Moore’s Law and densifying transistor counts.” The expected integration of these materials paves the way for a trillion-transistor GPU, setting a new standard for chip manufacturing.
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