SiFive Launches New RISC-V Chip Design Optimized for High-Performance AI Applications

SiFive, a leader in RISC-V chip design, has unveiled its latest AI chip lineup, the SiFive Intelligence XM Series, specifically engineered to enhance high-performance AI workloads.

Innovating AI Solutions

The XM Series features a highly scalable AI matrix engine that accelerates time-to-market for semiconductor companies developing system-on-chip solutions for edge IoT, consumer devices, next-generation electric or autonomous vehicles, and data centers.

Open Source Commitment

As part of its strategy to support the RISC-V ecosystem, SiFive announced plans to open source a reference implementation of its SiFive Kernel Library (SKL) during a press event held in Santa Clara. Executives highlighted RISC-V’s pivotal role in powering AI solutions for various market leaders and offered insights into SiFive’s strategic roadmap and business progress.

CEO Insights

Patrick Little, CEO of SiFive, emphasized the appreciation from semiconductor and consumer markets for SiFive's software strategy. Little reported that over 10 billion SiFive cores have been shipped, and the company has invested more than $500 million in R&D, boasting over 400 design wins among leading semiconductor firms and hyperscalers.

Versatile RISC-V Architecture

SiFive’s RISC-V architecture features an open standard software interface, allowing customers to select their accelerators for AI applications without the risk of software compatibility issues. This flexibility enables smaller companies to compete alongside larger players like Nvidia, who utilize proprietary GPU architectures. As a result, hyperscalers and chip manufacturers increasingly favor RISC-V solutions to ensure software longevity and compatibility as AI accelerators evolve.

Filling the AI Gap

SiFive has evolved from embedded cores since the 1990s to vector processors in 2021, and is now introducing AI solutions. Its architecture enables customers to deploy a data flow processor at the frontend, accommodating rapidly changing AI accelerators.

“We provide a stable platform for AI development,” said Little. “With the introduction of our new matrix multiplication engine in the XM Series, we complement our vector processing capabilities.”

Competitive Edge Against Nvidia

Little noted that companies seeking alternatives to Nvidia prefer RISC-V to avoid proprietary solutions, highlighting that RISC-V's competitive landscape benefits potential users. “We believe our solution can match Nvidia’s performance levels,” he asserted.

“Many companies are recognizing the advantages of an open processor standard in keeping pace with AI advancements. SiFive excels in performance per watt and custom solution development,” he added. “We’re already catering to five of the leading 'Magnificent 7' companies and are collaborating on new AI solutions spanning automotive, data centers, intelligent edge, and IoT segments.”

XM Series Features

The XM Series is distinguished by its scalable and efficient AI compute engine, integrating scalar, vector, and matrix engines to optimize memory bandwidth while maintaining high performance per watt for compute-intensive tasks.

Krste Asanovic, SiFive's chief architect, indicated that RISC-V was designed to support specialized computing engines, which is part of why leading data center firms are adopting RISC-V AI accelerators.

Technical Specifications

The XM Series features clusters with four X-Cores each, capable of delivering 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz. Each cluster boasts 1TB/s of sustained memory bandwidth, and can access memory through high-bandwidth or CHI ports for coherent memory access. SiFive envisions systems with no host CPU or those based on RISC-V, x86, or Arm architectures. The company is currently sampling its solutions.

Upcoming Event

SiFive will participate in the RISC-V Summit North America on October 22-23, 2024, in Santa Clara, California. With a team of 500 employees, SiFive continues to set the standard in RISC-V chip design. Little stated, “We’ve become the gold standard of RISC-V.”

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